//* ----------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//* ----------------------------------------------------------------------------
//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//* ----------------------------------------------------------------------------
//* File Name           : lib_AT91SAM7S64.h
//* Object              : AT91SAM7S64 inlined functions
//* Generated           : AT91 SW Application Group  08/30/2005 (15:52:59)
//*
//* CVS Reference       : /lib_dbgu.h/1.1/Thu Aug 25 12:56:22 2005//
//* CVS Reference       : /lib_pmc_SAM7S.h/1.4/Tue Aug 30 13:00:43 2005//
//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
//* CVS Reference       : /lib_spi2.h/1.2/Tue Aug 23 15:37:28 2005//
//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
//* CVS Reference       : /lib_aic_6075b.h/1.2/Thu Jul  7 07:48:22 2005//
//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
//* CVS Reference       : /lib_udp.h/1.5/Tue Aug 30 12:13:47 2005//
//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
//* CVS Reference       : /lib_MC_SAM7S.h/1.1/Thu Mar 25 15:19:14 2004//
//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
//* ----------------------------------------------------------------------------

#ifndef lib_AT91SAM7_H
#define lib_AT91SAM7_H

#include <AT91SAM7.h>

typedef void (*THandler) (void);

/* *****************************************************************************
                SOFTWARE API FOR AIC
   ***************************************************************************** */
#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20)	// ldr, pc, [pc, #-&F20]

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_ConfigureIt
//* \brief Interrupt Handler Initialization
//*----------------------------------------------------------------------------
extern unsigned int AT91F_AIC_ConfigureIt (unsigned int irq_id,	// \arg interrupt number to initialize
					   unsigned int priority,	// \arg priority to give to the interrupt
					   unsigned int src_type,	// \arg activation and sense of activation
					   THandler handler);	// \arg address of the interrupt handler

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_EnableIt
//* \brief Enable corresponding IT number
//*----------------------------------------------------------------------------
static inline void
AT91F_AIC_EnableIt (unsigned int irq_id)	// \arg interrupt number to initialize
{
  //* Enable the interrupt on the interrupt controller
  AT91C_BASE_AIC->AIC_IECR = 0x1 << irq_id;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_DisableIt
//* \brief Disable corresponding IT number
//*----------------------------------------------------------------------------
static inline void
AT91F_AIC_DisableIt (unsigned int irq_id)	// \arg interrupt number to initialize
{
  unsigned int mask = 0x1 << irq_id;
  //* Disable the interrupt on the interrupt controller
  AT91C_BASE_AIC->AIC_IDCR = mask;
  //* Clear the interrupt on the Interrupt Controller ( if one is pending )
  AT91C_BASE_AIC->AIC_ICCR = mask;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_ClearIt
//* \brief Clear corresponding IT number
//*----------------------------------------------------------------------------
static inline void
AT91F_AIC_ClearIt (unsigned int irq_id)	// \arg interrupt number to initialize
{
  //* Clear the interrupt on the Interrupt Controller ( if one is pending )
  AT91C_BASE_AIC->AIC_ICCR = (0x1 << irq_id);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_AcknowledgeIt
//* \brief Acknowledge corresponding IT number
//*----------------------------------------------------------------------------
static inline void
AT91F_AIC_AcknowledgeIt (void)
{
  AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_AIC->AIC_EOICR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_SetExceptionVector
//* \brief Configure vector handler
//*----------------------------------------------------------------------------
extern unsigned int AT91F_AIC_SetExceptionVector (unsigned int *pVector,	// \arg pointer to the AIC registers
						  THandler Handler);	// \arg Interrupt Handler

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_Trig
//* \brief Trig an IT
//*----------------------------------------------------------------------------
static inline void
AT91F_AIC_Trig (AT91PS_AIC pAic,	// \arg pointer to the AIC registers
		unsigned int irq_id)	// \arg interrupt number
{
  pAic->AIC_ISCR = (0x1 << irq_id);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_IsActive
//* \brief Test if an IT is active
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_AIC_IsActive (AT91PS_AIC pAic,	// \arg pointer to the AIC registers
		    unsigned int irq_id)	// \arg Interrupt Number
{
  return (pAic->AIC_ISR & (0x1 << irq_id));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_IsPending
//* \brief Test if an IT is pending
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_AIC_IsPending (AT91PS_AIC pAic,	// \arg pointer to the AIC registers
		     unsigned int irq_id)	// \arg Interrupt Number
{
  return (pAic->AIC_IPR & (0x1 << irq_id));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_Open
//* \brief Set exception vectors and AIC registers to default values
//*----------------------------------------------------------------------------
extern void AT91F_AIC_Open (THandler IrqHandler,	// \arg Default IRQ vector exception
			    THandler FiqHandler,	// \arg Default FIQ vector exception
			    THandler DefaultHandler,	// \arg Default Handler set in ISR
			    THandler SpuriousHandler,	// \arg Default Spurious Handler
			    unsigned int protectMode);	// \arg Debug Control Register

/* *****************************************************************************
                SOFTWARE API FOR PDC
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_SetNextRx
//* \brief Set the next receive transfer descriptor
//*----------------------------------------------------------------------------
static inline void
AT91F_PDC_SetNextRx (AT91PS_PDC pPDC,	// \arg pointer to a PDC controller
		     unsigned char *address,	// \arg address to the next bloc to be received
		     unsigned int bytes)	// \arg number of bytes to be received
{
  pPDC->PDC_RNPR = (unsigned int) address;
  pPDC->PDC_RNCR = bytes;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_SetNextTx
//* \brief Set the next transmit transfer descriptor
//*----------------------------------------------------------------------------
static inline void
AT91F_PDC_SetNextTx (AT91PS_PDC pPDC,	// \arg pointer to a PDC controller
		     const unsigned char *address,	// \arg address to the next bloc to be transmitted
		     unsigned int bytes)	// \arg number of bytes to be transmitted
{
  pPDC->PDC_TNPR = (unsigned int) address;
  pPDC->PDC_TNCR = bytes;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_SetRx
//* \brief Set the receive transfer descriptor
//*----------------------------------------------------------------------------
static inline void
AT91F_PDC_SetRx (AT91PS_PDC pPDC,	// \arg pointer to a PDC controller
		 unsigned char *address,	// \arg address to the next bloc to be received
		 unsigned int bytes)	// \arg number of bytes to be received
{
  pPDC->PDC_RPR = (unsigned int) address;
  pPDC->PDC_RCR = bytes;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_SetTx
//* \brief Set the transmit transfer descriptor
//*----------------------------------------------------------------------------
static inline void
AT91F_PDC_SetTx (AT91PS_PDC pPDC,	// \arg pointer to a PDC controller
		 const unsigned char *address,	// \arg address to the next bloc to be transmitted
		 unsigned int bytes)	// \arg number of bytes to be transmitted
{
  pPDC->PDC_TPR = (unsigned int) address;
  pPDC->PDC_TCR = bytes;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_EnableTx
//* \brief Enable transmit
//*----------------------------------------------------------------------------
static inline void
AT91F_PDC_EnableTx (AT91PS_PDC pPDC)	// \arg pointer to a PDC controller
{
  pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_EnableRx
//* \brief Enable receive
//*----------------------------------------------------------------------------
static inline void
AT91F_PDC_EnableRx (AT91PS_PDC pPDC)	// \arg pointer to a PDC controller
{
  pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_DisableTx
//* \brief Disable transmit
//*----------------------------------------------------------------------------
static inline void
AT91F_PDC_DisableTx (AT91PS_PDC pPDC)	// \arg pointer to a PDC controller
{
  pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_DisableRx
//* \brief Disable receive
//*----------------------------------------------------------------------------
static inline void
AT91F_PDC_DisableRx (AT91PS_PDC pPDC)	// \arg pointer to a PDC controller
{
  pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_IsTxEmpty
//* \brief Test if the current transfer descriptor has been sent
//*----------------------------------------------------------------------------
static inline int
AT91F_PDC_IsTxEmpty (		// \return return 1 if transfer is complete
		      AT91PS_PDC pPDC)	// \arg pointer to a PDC controller
{
  return !(pPDC->PDC_TCR);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_IsNextTxEmpty
//* \brief Test if the next transfer descriptor has been moved to the current td
//*----------------------------------------------------------------------------
static inline int
AT91F_PDC_IsNextTxEmpty (	// \return return 1 if transfer is complete
			  AT91PS_PDC pPDC)	// \arg pointer to a PDC controller
{
  return !(pPDC->PDC_TNCR);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_IsRxEmpty
//* \brief Test if the current transfer descriptor has been filled
//*----------------------------------------------------------------------------
static inline int
AT91F_PDC_IsRxEmpty (		// \return return 1 if transfer is complete
		      AT91PS_PDC pPDC)	// \arg pointer to a PDC controller
{
  return !(pPDC->PDC_RCR);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_IsNextRxEmpty
//* \brief Test if the next transfer descriptor has been moved to the current td
//*----------------------------------------------------------------------------
static inline int
AT91F_PDC_IsNextRxEmpty (	// \return return 1 if transfer is complete
			  AT91PS_PDC pPDC)	// \arg pointer to a PDC controller
{
  return !(pPDC->PDC_RNCR);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_Open
//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
//*----------------------------------------------------------------------------
extern void AT91F_PDC_Open (AT91PS_PDC pPDC);	// \arg pointer to a PDC controller

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_Close
//* \brief Close PDC: disable TX and RX reset transfer descriptors
//*----------------------------------------------------------------------------
extern void AT91F_PDC_Close (AT91PS_PDC pPDC);	// \arg pointer to a PDC controller

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_SendFrame
//* \brief Close PDC: disable TX and RX reset transfer descriptors
//*----------------------------------------------------------------------------
extern unsigned int AT91F_PDC_SendFrame (AT91PS_PDC pPDC,
					 const unsigned char *pBuffer,
					 unsigned int szBuffer,
					 const unsigned char *pNextBuffer,
					 unsigned int szNextBuffer);

//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_ReceiveFrame
//* \brief Close PDC: disable TX and RX reset transfer descriptors
//*----------------------------------------------------------------------------
extern unsigned int AT91F_PDC_ReceiveFrame (AT91PS_PDC pPDC,
					    unsigned char *pBuffer,
					    unsigned int szBuffer,
					    unsigned char *pNextBuffer,
					    unsigned int szNextBuffer);

/* *****************************************************************************
                SOFTWARE API FOR DBGU
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_DBGU_InterruptEnable
//* \brief Enable DBGU Interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_DBGU_InterruptEnable (AT91PS_DBGU pDbgu,	// \arg  pointer to a DBGU controller
			    unsigned int flag)	// \arg  dbgu interrupt to be enabled
{
  pDbgu->DBGU_IER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_DBGU_InterruptDisable
//* \brief Disable DBGU Interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_DBGU_InterruptDisable (AT91PS_DBGU pDbgu,	// \arg  pointer to a DBGU controller
			     unsigned int flag)	// \arg  dbgu interrupt to be disabled
{
  pDbgu->DBGU_IDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_DBGU_GetInterruptMaskStatus
//* \brief Return DBGU Interrupt Mask Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_DBGU_GetInterruptMaskStatus (	// \return DBGU Interrupt Mask Status
				    AT91PS_DBGU pDbgu)	// \arg  pointer to a DBGU controller
{
  return pDbgu->DBGU_IMR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_DBGU_IsInterruptMasked
//* \brief Test if DBGU Interrupt is Masked 
//*----------------------------------------------------------------------------
static inline int
AT91F_DBGU_IsInterruptMasked (AT91PS_DBGU pDbgu,	// \arg  pointer to a DBGU controller
			      unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_DBGU_GetInterruptMaskStatus (pDbgu) & flag);
}

/* *****************************************************************************
                SOFTWARE API FOR PIO
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_CfgPeriph
//* \brief Enable pins to be drived by peripheral
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_CfgPeriph (AT91PS_PIO pPio,	// \arg pointer to a PIO controller
		     unsigned int periphAEnable,	// \arg PERIPH A to enable
		     unsigned int periphBEnable)	// \arg PERIPH B to enable
{
  pPio->PIO_ASR = periphAEnable;
  pPio->PIO_BSR = periphBEnable;
  pPio->PIO_PDR = (periphAEnable | periphBEnable);	// Set in Periph mode
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_CfgOutput
//* \brief Enable PIO in output mode
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_CfgOutput (AT91PS_PIO pPio,	// \arg pointer to a PIO controller
		     unsigned int pioEnable)	// \arg PIO to be enabled
{
  pPio->PIO_PER = pioEnable;	// Set in PIO mode
  pPio->PIO_OER = pioEnable;	// Configure in Output
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_CfgInput
//* \brief Enable PIO in input mode
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_CfgInput (AT91PS_PIO pPio,	// \arg pointer to a PIO controller
		    unsigned int inputEnable)	// \arg PIO to be enabled
{
  // Disable output
  pPio->PIO_ODR = inputEnable;
  pPio->PIO_PER = inputEnable;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_CfgOpendrain
//* \brief Configure PIO in open drain
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_CfgOpendrain (AT91PS_PIO pPio,	// \arg pointer to a PIO controller
			unsigned int multiDrvEnable)	// \arg pio to be configured in open drain
{
  // Configure the multi-drive option
  pPio->PIO_MDDR = ~multiDrvEnable;
  pPio->PIO_MDER = multiDrvEnable;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_CfgPullup
//* \brief Enable pullup on PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_CfgPullup (AT91PS_PIO pPio,	// \arg pointer to a PIO controller
		     unsigned int pullupEnable)	// \arg enable pullup on PIO
{
  // Connect or not Pullup
  pPio->PIO_PPUDR = ~pullupEnable;
  pPio->PIO_PPUER = pullupEnable;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_CfgDirectDrive
//* \brief Enable direct drive on PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_CfgDirectDrive (AT91PS_PIO pPio,	// \arg pointer to a PIO controller
			  unsigned int directDrive)	// \arg PIO to be configured with direct drive
{
  // Configure the Direct Drive
  pPio->PIO_OWDR = ~directDrive;
  pPio->PIO_OWER = directDrive;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_CfgInputFilter
//* \brief Enable input filter on input PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_CfgInputFilter (AT91PS_PIO pPio,	// \arg pointer to a PIO controller
			  unsigned int inputFilter)	// \arg PIO to be configured with input filter
{
  // Configure the Direct Drive
  pPio->PIO_IFDR = ~inputFilter;
  pPio->PIO_IFER = inputFilter;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_GetInput
//* \brief Return PIO input value
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PIO_GetInput (		// \return PIO input
		     AT91PS_PIO pPio)	// \arg  pointer to a PIO controller
{
  return pPio->PIO_PDSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_IsInputSet
//* \brief Test if PIO is input flag is active
//*----------------------------------------------------------------------------
static inline int
AT91F_PIO_IsInputSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
		      unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PIO_GetInput (pPio) & flag);
}


//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_SetOutput
//* \brief Set to 1 output PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_SetOutput (const AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
		     const unsigned int flag)	// \arg  output to be set
{
  pPio->PIO_SODR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_ClearOutput
//* \brief Set to 0 output PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_ClearOutput (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
		       unsigned int flag)	// \arg  output to be cleared
{
  pPio->PIO_CODR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_ForceOutput
//* \brief Force output when Direct drive option is enabled
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_ForceOutput (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
		       unsigned int flag)	// \arg  output to be forced
{
  pPio->PIO_ODSR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_Enable
//* \brief Enable PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_Enable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
		  unsigned int flag)	// \arg  pio to be enabled 
{
  pPio->PIO_PER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_Disable
//* \brief Disable PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_Disable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
		   unsigned int flag)	// \arg  pio to be disabled 
{
  pPio->PIO_PDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_GetStatus
//* \brief Return PIO Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PIO_GetStatus (		// \return PIO Status
		      AT91PS_PIO pPio)	// \arg  pointer to a PIO controller
{
  return pPio->PIO_PSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_IsSet
//* \brief Test if PIO is Set
//*----------------------------------------------------------------------------
static inline int
AT91F_PIO_IsSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
		 unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PIO_GetStatus (pPio) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_OutputEnable
//* \brief Output Enable PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_OutputEnable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			unsigned int flag)	// \arg  pio output to be enabled
{
  pPio->PIO_OER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_OutputDisable
//* \brief Output Enable PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_OutputDisable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			 unsigned int flag)	// \arg  pio output to be disabled
{
  pPio->PIO_ODR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_GetOutputStatus
//* \brief Return PIO Output Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PIO_GetOutputStatus (	// \return PIO Output Status
			    AT91PS_PIO pPio)	// \arg  pointer to a PIO controller
{
  return pPio->PIO_OSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_IsOuputSet
//* \brief Test if PIO Output is Set
//*----------------------------------------------------------------------------
static inline int
AT91F_PIO_IsOutputSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
		       unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PIO_GetOutputStatus (pPio) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_InputFilterEnable
//* \brief Input Filter Enable PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_InputFilterEnable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			     unsigned int flag)	// \arg  pio input filter to be enabled
{
  pPio->PIO_IFER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_InputFilterDisable
//* \brief Input Filter Disable PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_InputFilterDisable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			      unsigned int flag)	// \arg  pio input filter to be disabled
{
  pPio->PIO_IFDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_GetInputFilterStatus
//* \brief Return PIO Input Filter Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PIO_GetInputFilterStatus (	// \return PIO Input Filter Status
				 AT91PS_PIO pPio)	// \arg  pointer to a PIO controller
{
  return pPio->PIO_IFSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_IsInputFilterSet
//* \brief Test if PIO Input filter is Set
//*----------------------------------------------------------------------------
static inline int
AT91F_PIO_IsInputFilterSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			    unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PIO_GetInputFilterStatus (pPio) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_GetOutputDataStatus
//* \brief Return PIO Output Data Status 
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PIO_GetOutputDataStatus (	// \return PIO Output Data Status 
				AT91PS_PIO pPio)	// \arg  pointer to a PIO controller
{
  return pPio->PIO_ODSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_InterruptEnable
//* \brief Enable PIO Interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_InterruptEnable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			   unsigned int flag)	// \arg  pio interrupt to be enabled
{
  pPio->PIO_IER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_InterruptDisable
//* \brief Disable PIO Interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_InterruptDisable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			    unsigned int flag)	// \arg  pio interrupt to be disabled
{
  pPio->PIO_IDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_GetInterruptMaskStatus
//* \brief Return PIO Interrupt Mask Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PIO_GetInterruptMaskStatus (	// \return PIO Interrupt Mask Status
				   AT91PS_PIO pPio)	// \arg  pointer to a PIO controller
{
  return pPio->PIO_IMR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_GetInterruptStatus
//* \brief Return PIO Interrupt Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PIO_GetInterruptStatus (	// \return PIO Interrupt Status
			       AT91PS_PIO pPio)	// \arg  pointer to a PIO controller
{
  return pPio->PIO_ISR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_IsInterruptMasked
//* \brief Test if PIO Interrupt is Masked 
//*----------------------------------------------------------------------------
static inline int
AT91F_PIO_IsInterruptMasked (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			     unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PIO_GetInterruptMaskStatus (pPio) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_IsInterruptSet
//* \brief Test if PIO Interrupt is Set
//*----------------------------------------------------------------------------
static inline int
AT91F_PIO_IsInterruptSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			  unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PIO_GetInterruptStatus (pPio) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_MultiDriverEnable
//* \brief Multi Driver Enable PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_MultiDriverEnable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			     unsigned int flag)	// \arg  pio to be enabled
{
  pPio->PIO_MDER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_MultiDriverDisable
//* \brief Multi Driver Disable PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_MultiDriverDisable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			      unsigned int flag)	// \arg  pio to be disabled
{
  pPio->PIO_MDDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_GetMultiDriverStatus
//* \brief Return PIO Multi Driver Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PIO_GetMultiDriverStatus (	// \return PIO Multi Driver Status
				 AT91PS_PIO pPio)	// \arg  pointer to a PIO controller
{
  return pPio->PIO_MDSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_IsMultiDriverSet
//* \brief Test if PIO MultiDriver is Set
//*----------------------------------------------------------------------------
static inline int
AT91F_PIO_IsMultiDriverSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			    unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PIO_GetMultiDriverStatus (pPio) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_A_RegisterSelection
//* \brief PIO A Register Selection 
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_A_RegisterSelection (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			       unsigned int flag)	// \arg  pio A register selection
{
  pPio->PIO_ASR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_B_RegisterSelection
//* \brief PIO B Register Selection 
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_B_RegisterSelection (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			       unsigned int flag)	// \arg  pio B register selection 
{
  pPio->PIO_BSR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_Get_AB_RegisterStatus
//* \brief Return PIO Interrupt Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PIO_Get_AB_RegisterStatus (	// \return PIO AB Register Status
				  AT91PS_PIO pPio)	// \arg  pointer to a PIO controller
{
  return pPio->PIO_ABSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_IsAB_RegisterSet
//* \brief Test if PIO AB Register is Set
//*----------------------------------------------------------------------------
static inline int
AT91F_PIO_IsAB_RegisterSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			    unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PIO_Get_AB_RegisterStatus (pPio) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_OutputWriteEnable
//* \brief Output Write Enable PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_OutputWriteEnable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			     unsigned int flag)	// \arg  pio output write to be enabled
{
  pPio->PIO_OWER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_OutputWriteDisable
//* \brief Output Write Disable PIO
//*----------------------------------------------------------------------------
static inline void
AT91F_PIO_OutputWriteDisable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			      unsigned int flag)	// \arg  pio output write to be disabled
{
  pPio->PIO_OWDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_GetOutputWriteStatus
//* \brief Return PIO Output Write Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PIO_GetOutputWriteStatus (	// \return PIO Output Write Status
				 AT91PS_PIO pPio)	// \arg  pointer to a PIO controller
{
  return pPio->PIO_OWSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_IsOutputWriteSet
//* \brief Test if PIO OutputWrite is Set
//*----------------------------------------------------------------------------
static inline int
AT91F_PIO_IsOutputWriteSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
			    unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PIO_GetOutputWriteStatus (pPio) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_GetCfgPullup
//* \brief Return PIO Configuration Pullup
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PIO_GetCfgPullup (	// \return PIO Configuration Pullup 
			 AT91PS_PIO pPio)	// \arg  pointer to a PIO controller
{
  return pPio->PIO_PPUSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_IsOutputDataStatusSet
//* \brief Test if PIO Output Data Status is Set 
//*----------------------------------------------------------------------------
static inline int
AT91F_PIO_IsOutputDataStatusSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
				 unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PIO_GetOutputDataStatus (pPio) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIO_IsCfgPullupStatusSet
//* \brief Test if PIO Configuration Pullup Status is Set
//*----------------------------------------------------------------------------
static inline int
AT91F_PIO_IsCfgPullupStatusSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller
				unsigned int flag)	// \arg  flag to be tested
{
  return (~AT91F_PIO_GetCfgPullup (pPio) & flag);
}

/* *****************************************************************************
                SOFTWARE API FOR PMC
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_CfgSysClkEnableReg
//* \brief Configure the System Clock Enable Register of the PMC controller
//*----------------------------------------------------------------------------
static inline void
AT91F_PMC_CfgSysClkEnableReg (AT91PS_PMC pPMC,	// \arg pointer to PMC controller
			      unsigned int mode)
{
  //* Write to the SCER register
  pPMC->PMC_SCER = mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_CfgSysClkDisableReg
//* \brief Configure the System Clock Disable Register of the PMC controller
//*----------------------------------------------------------------------------
static inline void
AT91F_PMC_CfgSysClkDisableReg (AT91PS_PMC pPMC,	// \arg pointer to PMC controller
			       unsigned int mode)
{
  //* Write to the SCDR register
  pPMC->PMC_SCDR = mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_GetSysClkStatusReg
//* \brief Return the System Clock Status Register of the PMC controller
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PMC_GetSysClkStatusReg (AT91PS_PMC pPMC	// pointer to a CAN controller
  )
{
  return pPMC->PMC_SCSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_EnablePeriphClock
//* \brief Enable peripheral clock
//*----------------------------------------------------------------------------
static inline void
AT91F_PMC_EnablePeriphClock (AT91PS_PMC pPMC,	// \arg pointer to PMC controller
			     unsigned int periphIds)	// \arg IDs of peripherals to enable
{
  pPMC->PMC_PCER = periphIds;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_DisablePeriphClock
//* \brief Disable peripheral clock
//*----------------------------------------------------------------------------
static inline void
AT91F_PMC_DisablePeriphClock (AT91PS_PMC pPMC,	// \arg pointer to PMC controller
			      unsigned int periphIds)	// \arg IDs of peripherals to enable
{
  pPMC->PMC_PCDR = periphIds;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_GetPeriphClock
//* \brief Get peripheral clock status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PMC_GetPeriphClock (AT91PS_PMC pPMC)	// \arg pointer to PMC controller
{
  return pPMC->PMC_PCSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_CfgMainOscillatorReg
//* \brief Cfg the main oscillator
//*----------------------------------------------------------------------------
static inline void
AT91F_CKGR_CfgMainOscillatorReg (AT91PS_CKGR pCKGR,	// \arg pointer to CKGR controller
				 unsigned int mode)
{
  pCKGR->CKGR_MOR = mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_GetMainOscillatorReg
//* \brief Cfg the main oscillator
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_CKGR_GetMainOscillatorReg (AT91PS_CKGR pCKGR)	// \arg pointer to CKGR controller
{
  return pCKGR->CKGR_MOR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_EnableMainOscillator
//* \brief Enable the main oscillator
//*----------------------------------------------------------------------------
static inline void
AT91F_CKGR_EnableMainOscillator (AT91PS_CKGR pCKGR)	// \arg pointer to CKGR controller
{
  pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_DisableMainOscillator
//* \brief Disable the main oscillator
//*----------------------------------------------------------------------------
static inline void
AT91F_CKGR_DisableMainOscillator (AT91PS_CKGR pCKGR)	// \arg pointer to CKGR controller
{
  pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
//* \brief Cfg MOR Register according to the main osc startup time
//*----------------------------------------------------------------------------
static inline void
AT91F_CKGR_CfgMainOscStartUpTime (AT91PS_CKGR pCKGR,	// \arg pointer to CKGR controller
				  unsigned int startup_time,	// \arg main osc startup time in microsecond (us)
				  unsigned int slowClock)	// \arg slowClock in Hz
{
  pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
  pCKGR->CKGR_MOR |= ((slowClock * startup_time) / (8 * 1000000)) << 8;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_GetMainClockFreqReg
//* \brief Cfg the main oscillator
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_CKGR_GetMainClockFreqReg (AT91PS_CKGR pCKGR)	// \arg pointer to CKGR controller
{
  return pCKGR->CKGR_MCFR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_GetMainClock
//* \brief Return Main clock in Hz
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_CKGR_GetMainClock (AT91PS_CKGR pCKGR,	// \arg pointer to CKGR controller
			 unsigned int slowClock)	// \arg slowClock in Hz
{
  return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_CfgMCKReg
//* \brief Cfg Master Clock Register
//*----------------------------------------------------------------------------
static inline void
AT91F_PMC_CfgMCKReg (AT91PS_PMC pPMC,	// \arg pointer to PMC controller
		     unsigned int mode)
{
  pPMC->PMC_MCKR = mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_GetMCKReg
//* \brief Return Master Clock Register
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PMC_GetMCKReg (AT91PS_PMC pPMC)	// \arg pointer to PMC controller
{
  return pPMC->PMC_MCKR;
}

//*------------------------------------------------------------------------------
//* \fn    AT91F_PMC_GetMasterClock
//* \brief Return master clock in Hz which correponds to processor clock for ARM7
//*------------------------------------------------------------------------------
extern unsigned int AT91F_PMC_GetMasterClock (AT91PS_PMC pPMC,	// \arg pointer to PMC controller
					      AT91PS_CKGR pCKGR,	// \arg pointer to CKGR controller
					      unsigned int slowClock);	// \arg slowClock in Hz

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_EnablePCK
//* \brief Enable peripheral clock
//*----------------------------------------------------------------------------
static inline void
AT91F_PMC_EnablePCK (AT91PS_PMC pPMC,	// \arg pointer to PMC controller
		     unsigned int pck,	// \arg Peripheral clock identifier 0 .. 7
		     unsigned int mode)
{
  pPMC->PMC_PCKR[pck] = mode;
  pPMC->PMC_SCER = (1 << pck) << 8;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_DisablePCK
//* \brief Enable peripheral clock
//*----------------------------------------------------------------------------
static inline void
AT91F_PMC_DisablePCK (AT91PS_PMC pPMC,	// \arg pointer to PMC controller
		      unsigned int pck)	// \arg Peripheral clock identifier 0 .. 7
{
  pPMC->PMC_SCDR = (1 << pck) << 8;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_EnableIt
//* \brief Enable PMC interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_PMC_EnableIt (AT91PS_PMC pPMC,	// pointer to a PMC controller
		    unsigned int flag)	// IT to be enabled
{
  //* Write to the IER register
  pPMC->PMC_IER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_DisableIt
//* \brief Disable PMC interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_PMC_DisableIt (AT91PS_PMC pPMC,	// pointer to a PMC controller
		     unsigned int flag)	// IT to be disabled
{
  //* Write to the IDR register
  pPMC->PMC_IDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_GetStatus
//* \brief Return PMC Interrupt Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PMC_GetStatus (		// \return PMC Interrupt Status
		      AT91PS_PMC pPMC)	// pointer to a PMC controller
{
  return pPMC->PMC_SR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_GetInterruptMaskStatus
//* \brief Return PMC Interrupt Mask Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PMC_GetInterruptMaskStatus (	// \return PMC Interrupt Mask Status
				   AT91PS_PMC pPMC)	// pointer to a PMC controller
{
  return pPMC->PMC_IMR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_IsInterruptMasked
//* \brief Test if PMC Interrupt is Masked
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PMC_IsInterruptMasked (AT91PS_PMC pPMC,	// \arg  pointer to a PMC controller
			     unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PMC_GetInterruptMaskStatus (pPMC) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_IsStatusSet
//* \brief Test if PMC Status is Set
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PMC_IsStatusSet (AT91PS_PMC pPMC,	// \arg  pointer to a PMC controller
		       unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PMC_GetStatus (pPMC) & flag);
}

// ----------------------------------------------------------------------------
//  \fn    AT91F_CKGR_CfgPLLReg
//  \brief Cfg the PLL Register
// ----------------------------------------------------------------------------
static inline void
AT91F_CKGR_CfgPLLReg (AT91PS_CKGR pCKGR,	// \arg pointer to CKGR controller
		      unsigned int mode)
{
  pCKGR->CKGR_PLLR = mode;
}

// ----------------------------------------------------------------------------
//  \fn    AT91F_CKGR_GetPLLReg
//  \brief Get the PLL Register
// ----------------------------------------------------------------------------
static inline unsigned int
AT91F_CKGR_GetPLLReg (AT91PS_CKGR pCKGR)	// \arg pointer to CKGR controller
{
  return pCKGR->CKGR_PLLR;
}



/* *****************************************************************************
                SOFTWARE API FOR RSTC
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_RSTSoftReset
//* \brief Start Software Reset
//*----------------------------------------------------------------------------
static inline void
AT91F_RSTSoftReset (AT91PS_RSTC pRSTC, unsigned int reset)
{
  pRSTC->RSTC_RCR = (0xA5000000 | reset);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_RSTSetMode
//* \brief Set Reset Mode
//*----------------------------------------------------------------------------
static inline void
AT91F_RSTSetMode (AT91PS_RSTC pRSTC, unsigned int mode)
{
  pRSTC->RSTC_RMR = (0xA5000000 | mode);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_RSTGetMode
//* \brief Get Reset Mode
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_RSTGetMode (AT91PS_RSTC pRSTC)
{
  return (pRSTC->RSTC_RMR);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_RSTGetStatus
//* \brief Get Reset Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_RSTGetStatus (AT91PS_RSTC pRSTC)
{
  return (pRSTC->RSTC_RSR);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_RSTIsSoftRstActive
//* \brief Return !=0 if software reset is still not completed
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_RSTIsSoftRstActive (AT91PS_RSTC pRSTC)
{
  return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
}

/* *****************************************************************************
                SOFTWARE API FOR RTTC
   ***************************************************************************** */
//*--------------------------------------------------------------------------------------
//* \fn     AT91F_SetRTT_TimeBase()
//* \brief  Set the RTT prescaler according to the TimeBase in ms
//*--------------------------------------------------------------------------------------
static inline unsigned int
AT91F_RTTSetTimeBase (AT91PS_RTTC pRTTC, unsigned int ms)
{
  if (ms > 2000)
    return 1;			// AT91C_TIME_OUT_OF_RANGE
  pRTTC->RTTC_RTMR &= ~0xFFFF;
  pRTTC->RTTC_RTMR |= (((ms << 15) / 1000) & 0xFFFF);
  return 0;
}

//*--------------------------------------------------------------------------------------
//* \fn     AT91F_RTTSetPrescaler()
//* \brief  Set the new prescaler value
//*--------------------------------------------------------------------------------------
static inline unsigned int
AT91F_RTTSetPrescaler (AT91PS_RTTC pRTTC, unsigned int rtpres)
{
  pRTTC->RTTC_RTMR &= ~0xFFFF;
  pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);
  return (pRTTC->RTTC_RTMR);
}

//*--------------------------------------------------------------------------------------
//* \fn     AT91F_RTTRestart()
//* \brief  Restart the RTT prescaler
//*--------------------------------------------------------------------------------------
static inline void
AT91F_RTTRestart (AT91PS_RTTC pRTTC)
{
  pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
}


//*--------------------------------------------------------------------------------------
//* \fn     AT91F_RTT_SetAlarmINT()
//* \brief  Enable RTT Alarm Interrupt
//*--------------------------------------------------------------------------------------
static inline void
AT91F_RTTSetAlarmINT (AT91PS_RTTC pRTTC)
{
  pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
}

//*--------------------------------------------------------------------------------------
//* \fn     AT91F_RTT_ClearAlarmINT()
//* \brief  Disable RTT Alarm Interrupt
//*--------------------------------------------------------------------------------------
static inline void
AT91F_RTTClearAlarmINT (AT91PS_RTTC pRTTC)
{
  pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
}

//*--------------------------------------------------------------------------------------
//* \fn     AT91F_RTT_SetRttIncINT()
//* \brief  Enable RTT INC Interrupt
//*--------------------------------------------------------------------------------------
static inline void
AT91F_RTTSetRttIncINT (AT91PS_RTTC pRTTC)
{
  pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
}

//*--------------------------------------------------------------------------------------
//* \fn     AT91F_RTT_ClearRttIncINT()
//* \brief  Disable RTT INC Interrupt
//*--------------------------------------------------------------------------------------
static inline void
AT91F_RTTClearRttIncINT (AT91PS_RTTC pRTTC)
{
  pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
}

//*--------------------------------------------------------------------------------------
//* \fn     AT91F_RTT_SetAlarmValue()
//* \brief  Set RTT Alarm Value
//*--------------------------------------------------------------------------------------
static inline void
AT91F_RTTSetAlarmValue (AT91PS_RTTC pRTTC, unsigned int _alarm)
{
  pRTTC->RTTC_RTAR = _alarm;
}

//*--------------------------------------------------------------------------------------
//* \fn     AT91F_RTT_GetAlarmValue()
//* \brief  Get RTT Alarm Value
//*--------------------------------------------------------------------------------------
static inline unsigned int
AT91F_RTTGetAlarmValue (AT91PS_RTTC pRTTC)
{
  return (pRTTC->RTTC_RTAR);
}

//*--------------------------------------------------------------------------------------
//* \fn     AT91F_RTTGetStatus()
//* \brief  Read the RTT status
//*--------------------------------------------------------------------------------------
static inline unsigned int
AT91F_RTTGetStatus (AT91PS_RTTC pRTTC)
{
  return (pRTTC->RTTC_RTSR);
}

//*--------------------------------------------------------------------------------------
//* \fn     AT91F_RTT_ReadValue()
//* \brief  Read the RTT value
//*--------------------------------------------------------------------------------------
extern unsigned int AT91F_RTTReadValue (AT91PS_RTTC pRTTC);

/* *****************************************************************************
                SOFTWARE API FOR PITC
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_PITInit
//* \brief System timer init : period in �second, system clock freq in MHz
//*----------------------------------------------------------------------------
static inline void
AT91F_PITInit (AT91PS_PITC pPITC,
	       unsigned int period, unsigned int pit_frequency)
{
  pPITC->PITC_PIMR = period ? (period * pit_frequency + 8) >> 4 : 0;	// +8 to avoid %10 and /10
  pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PITSetPIV
//* \brief Set the PIT Periodic Interval Value 
//*----------------------------------------------------------------------------
static inline void
AT91F_PITSetPIV (AT91PS_PITC pPITC, unsigned int piv)
{
  pPITC->PITC_PIMR =
    piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PITEnableInt
//* \brief Enable PIT periodic interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_PITEnableInt (AT91PS_PITC pPITC)
{
  pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PITDisableInt
//* \brief Disable PIT periodic interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_PITDisableInt (AT91PS_PITC pPITC)
{
  pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PITGetMode
//* \brief Read PIT mode register
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PITGetMode (AT91PS_PITC pPITC)
{
  return (pPITC->PITC_PIMR);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PITGetStatus
//* \brief Read PIT status register
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PITGetStatus (AT91PS_PITC pPITC)
{
  return (pPITC->PITC_PISR);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PITGetPIIR
//* \brief Read PIT CPIV and PICNT without ressetting the counters
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PITGetPIIR (AT91PS_PITC pPITC)
{
  return (pPITC->PITC_PIIR);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PITGetPIVR
//* \brief Read System timer CPIV and PICNT without ressetting the counters
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PITGetPIVR (AT91PS_PITC pPITC)
{
  return (pPITC->PITC_PIVR);
}

/* *****************************************************************************
                SOFTWARE API FOR WDTC
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_WDTSetMode
//* \brief Set Watchdog Mode Register
//*----------------------------------------------------------------------------
static inline void
AT91F_WDTSetMode (AT91PS_WDTC pWDTC, unsigned int Mode)
{
  pWDTC->WDTC_WDMR = Mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_WDTRestart
//* \brief Restart Watchdog
//*----------------------------------------------------------------------------
static inline void
AT91F_WDTRestart (AT91PS_WDTC pWDTC)
{
  pWDTC->WDTC_WDCR = 0xA5000001;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_WDTSGettatus
//* \brief Get Watchdog Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_WDTSGettatus (AT91PS_WDTC pWDTC)
{
  return (pWDTC->WDTC_WDSR & 0x3);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_WDTGetPeriod
//* \brief Translate ms into Watchdog Compatible value
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_WDTGetPeriod (unsigned int ms)
{
  if ((ms < 4) || (ms > 16000))
    return 0;
  return ((ms << 8) / 1000);
}

/* *****************************************************************************
                SOFTWARE API FOR VREG
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_VREG_Enable_LowPowerMode
//* \brief Enable VREG Low Power Mode
//*----------------------------------------------------------------------------
static inline void
AT91F_VREG_Enable_LowPowerMode (AT91PS_VREG pVREG)
{
  pVREG->VREG_MR |= AT91C_VREG_PSTDBY;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_VREG_Disable_LowPowerMode
//* \brief Disable VREG Low Power Mode
//*----------------------------------------------------------------------------
static inline void
AT91F_VREG_Disable_LowPowerMode (AT91PS_VREG pVREG)
{
  pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
}				/* *****************************************************************************
				   SOFTWARE API FOR MC
				   ***************************************************************************** */

#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24)	// (MC) Correct Protect Key

//*----------------------------------------------------------------------------
//* \fn    AT91F_MC_Remap
//* \brief Make Remap
//*----------------------------------------------------------------------------
static inline void
AT91F_MC_Remap (void)		//  
{
  AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;

  pMC->MC_RCR = AT91C_MC_RCB;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_MC_EFC_CfgModeReg
//* \brief Configure the EFC Mode Register of the MC controller
//*----------------------------------------------------------------------------
static inline void
AT91F_MC_EFC_CfgModeReg (AT91PS_MC pMC,	// pointer to a MC controller
			 unsigned int mode)	// mode register 
{
  // Write to the FMR register
  pMC->MC_FMR = mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_MC_EFC_GetModeReg
//* \brief Return MC EFC Mode Regsiter
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_MC_EFC_GetModeReg (AT91PS_MC pMC)	// pointer to a MC controller
{
  return pMC->MC_FMR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_MC_EFC_ComputeFMCN
//* \brief Return MC EFC Mode Regsiter
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_MC_EFC_ComputeFMCN (int master_clock)	// master clock in Hz
{
  return (master_clock / 1000000 + 2);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_MC_EFC_PerformCmd
//* \brief Perform EFC Command
//*----------------------------------------------------------------------------
static inline void
AT91F_MC_EFC_PerformCmd (AT91PS_MC pMC,	// pointer to a MC controller
			 unsigned int transfer_cmd)
{
  pMC->MC_FCR = transfer_cmd;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_MC_EFC_GetStatus
//* \brief Return MC EFC Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_MC_EFC_GetStatus (AT91PS_MC pMC)	// pointer to a MC controller
{
  return pMC->MC_FSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_MC_EFC_IsInterruptMasked
//* \brief Test if EFC MC Interrupt is Masked 
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_MC_EFC_IsInterruptMasked (AT91PS_MC pMC,	// \arg  pointer to a MC controller
				unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_MC_EFC_GetModeReg (pMC) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_MC_EFC_IsInterruptSet
//* \brief Test if EFC MC Interrupt is Set
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_MC_EFC_IsInterruptSet (AT91PS_MC pMC,	// \arg  pointer to a MC controller
			     unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_MC_EFC_GetStatus (pMC) & flag);
}

/* *****************************************************************************
                SOFTWARE API FOR SPI
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_CfgCs
//* \brief Configure SPI chip select register
//*----------------------------------------------------------------------------
static inline void
AT91F_SPI_CfgCs (AT91PS_SPI pSPI,	// pointer to a SPI controller
		 int cs,	// SPI cs number (0 to 3)
		 int val)	//  chip select register
{
  //* Write to the CSR register
  *(pSPI->SPI_CSR + cs) = val;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_EnableIt
//* \brief Enable SPI interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_SPI_EnableIt (AT91PS_SPI pSPI,	// pointer to a SPI controller
		    unsigned int flag)	// IT to be enabled
{
  //* Write to the IER register
  pSPI->SPI_IER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_DisableIt
//* \brief Disable SPI interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_SPI_DisableIt (AT91PS_SPI pSPI,	// pointer to a SPI controller
		     unsigned int flag)	// IT to be disabled
{
  //* Write to the IDR register
  pSPI->SPI_IDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_Reset
//* \brief Reset the SPI controller
//*----------------------------------------------------------------------------
static inline void
AT91F_SPI_Reset (AT91PS_SPI pSPI	// pointer to a SPI controller
  )
{
  //* Write to the CR register
  pSPI->SPI_CR = AT91C_SPI_SWRST;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_Enable
//* \brief Enable the SPI controller
//*----------------------------------------------------------------------------
static inline void
AT91F_SPI_Enable (AT91PS_SPI pSPI	// pointer to a SPI controller
  )
{
  //* Write to the CR register
  pSPI->SPI_CR = AT91C_SPI_SPIEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_Disable
//* \brief Disable the SPI controller
//*----------------------------------------------------------------------------
static inline void
AT91F_SPI_Disable (AT91PS_SPI pSPI	// pointer to a SPI controller
  )
{
  //* Write to the CR register
  pSPI->SPI_CR = AT91C_SPI_SPIDIS;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_CfgMode
//* \brief Enable the SPI controller
//*----------------------------------------------------------------------------
static inline void
AT91F_SPI_CfgMode (AT91PS_SPI pSPI,	// pointer to a SPI controller
		   int mode)	// mode register 
{
  //* Write to the MR register
  pSPI->SPI_MR = mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_CfgPCS
//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
//*----------------------------------------------------------------------------
static inline void
AT91F_SPI_CfgPCS (AT91PS_SPI pSPI,	// pointer to a SPI controller
		  char PCS_Device)	// PCS of the Device
{
  //* Write to the MR register
  pSPI->SPI_MR &= 0xFFF0FFFF;
  pSPI->SPI_MR |= ((PCS_Device << 16) & AT91C_SPI_PCS);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_ReceiveFrame
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_SPI_ReceiveFrame (AT91PS_SPI pSPI,
			unsigned char *pBuffer,
			unsigned int szBuffer,
			unsigned char *pNextBuffer, unsigned int szNextBuffer)
{
  return AT91F_PDC_ReceiveFrame ((AT91PS_PDC) & (pSPI->SPI_RPR),
				 pBuffer,
				 szBuffer, pNextBuffer, szNextBuffer);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_SendFrame
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_SPI_SendFrame (AT91PS_SPI pSPI,
		     const unsigned char *pBuffer,
		     unsigned int szBuffer,
		     const unsigned char *pNextBuffer,
		     unsigned int szNextBuffer)
{
  return AT91F_PDC_SendFrame ((AT91PS_PDC) & (pSPI->SPI_RPR),
			      pBuffer, szBuffer, pNextBuffer, szNextBuffer);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_Close
//* \brief Close SPI: disable IT disable transfert, close PDC
//*----------------------------------------------------------------------------
extern void AT91F_SPI_Close (AT91PS_SPI pSPI);	// \arg pointer to a SPI controller

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_PutChar
//* \brief Send a character,does not check if ready to send
//*----------------------------------------------------------------------------
static inline void
AT91F_SPI_PutChar (AT91PS_SPI pSPI,
		   unsigned int character, unsigned int cs_number)
{
  unsigned int value_for_cs;
  value_for_cs = (~(1 << cs_number)) & 0xF;	//Place a zero among a 4 ONEs number
  pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_GetChar
//* \brief Receive a character,does not check if a character is available
//*----------------------------------------------------------------------------
static inline int
AT91F_SPI_GetChar (const AT91PS_SPI pSPI)
{
  return ((pSPI->SPI_RDR) & 0xFFFF);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_GetInterruptMaskStatus
//* \brief Return SPI Interrupt Mask Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_SPI_GetInterruptMaskStatus (	// \return SPI Interrupt Mask Status
				   AT91PS_SPI pSpi)	// \arg  pointer to a SPI controller
{
  return pSpi->SPI_IMR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_IsInterruptMasked
//* \brief Test if SPI Interrupt is Masked 
//*----------------------------------------------------------------------------
static inline int
AT91F_SPI_IsInterruptMasked (AT91PS_SPI pSpi,	// \arg  pointer to a SPI controller
			     unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_SPI_GetInterruptMaskStatus (pSpi) & flag);
}

/* *****************************************************************************
                SOFTWARE API FOR ADC
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_EnableIt
//* \brief Enable ADC interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_ADC_EnableIt (AT91PS_ADC pADC,	// pointer to a ADC controller
		    unsigned int flag)	// IT to be enabled
{
  //* Write to the IER register
  pADC->ADC_IER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_DisableIt
//* \brief Disable ADC interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_ADC_DisableIt (AT91PS_ADC pADC,	// pointer to a ADC controller
		     unsigned int flag)	// IT to be disabled
{
  //* Write to the IDR register
  pADC->ADC_IDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_GetStatus
//* \brief Return ADC Interrupt Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_GetStatus (		// \return ADC Interrupt Status
		      AT91PS_ADC pADC)	// pointer to a ADC controller
{
  return pADC->ADC_SR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_GetInterruptMaskStatus
//* \brief Return ADC Interrupt Mask Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_GetInterruptMaskStatus (	// \return ADC Interrupt Mask Status
				   AT91PS_ADC pADC)	// pointer to a ADC controller
{
  return pADC->ADC_IMR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_IsInterruptMasked
//* \brief Test if ADC Interrupt is Masked 
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_IsInterruptMasked (AT91PS_ADC pADC,	// \arg  pointer to a ADC controller
			     unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_ADC_GetInterruptMaskStatus (pADC) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_IsStatusSet
//* \brief Test if ADC Status is Set
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_IsStatusSet (AT91PS_ADC pADC,	// \arg  pointer to a ADC controller
		       unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_ADC_GetStatus (pADC) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_CfgModeReg
//* \brief Configure the Mode Register of the ADC controller
//*----------------------------------------------------------------------------
static inline void
AT91F_ADC_CfgModeReg (AT91PS_ADC pADC,	// pointer to a ADC controller
		      unsigned int mode)	// mode register 
{
  //* Write to the MR register
  pADC->ADC_MR = mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_GetModeReg
//* \brief Return the Mode Register of the ADC controller value
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_GetModeReg (AT91PS_ADC pADC	// pointer to a ADC controller
  )
{
  return pADC->ADC_MR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_CfgTimings
//* \brief Configure the different necessary timings of the ADC controller
//*----------------------------------------------------------------------------
extern void AT91F_ADC_CfgTimings (AT91PS_ADC pADC,	// pointer to a ADC controller
				  unsigned int mck_clock,	// in MHz 
				  unsigned int adc_clock,	// in MHz 
				  unsigned int startup_time,	// in us 
				  unsigned int sample_and_hold_time);	// in ns  

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_EnableChannel
//* \brief Return ADC Timer Register Value
//*----------------------------------------------------------------------------
static inline void
AT91F_ADC_EnableChannel (AT91PS_ADC pADC,	// pointer to a ADC controller
			 unsigned int channel)	// mode register 
{
  //* Write to the CHER register
  pADC->ADC_CHER = channel;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_DisableChannel
//* \brief Return ADC Timer Register Value
//*----------------------------------------------------------------------------
static inline void
AT91F_ADC_DisableChannel (AT91PS_ADC pADC,	// pointer to a ADC controller
			  unsigned int channel)	// mode register 
{
  //* Write to the CHDR register
  pADC->ADC_CHDR = channel;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_GetChannelStatus
//* \brief Return ADC Timer Register Value
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_GetChannelStatus (AT91PS_ADC pADC	// pointer to a ADC controller
  )
{
  return pADC->ADC_CHSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_StartConversion
//* \brief Software request for a analog to digital conversion 
//*----------------------------------------------------------------------------
static inline void
AT91F_ADC_StartConversion (AT91PS_ADC pADC	// pointer to a ADC controller
  )
{
  pADC->ADC_CR = AT91C_ADC_START;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_SoftReset
//* \brief Software reset
//*----------------------------------------------------------------------------
static inline void
AT91F_ADC_SoftReset (AT91PS_ADC pADC	// pointer to a ADC controller
  )
{
  pADC->ADC_CR = AT91C_ADC_SWRST;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_GetLastConvertedData
//* \brief Return the Last Converted Data
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_GetLastConvertedData (AT91PS_ADC pADC	// pointer to a ADC controller
  )
{
  return pADC->ADC_LCDR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_GetConvertedDataCH0
//* \brief Return the Channel 0 Converted Data
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_GetConvertedDataCH0 (AT91PS_ADC pADC	// pointer to a ADC controller
  )
{
  return pADC->ADC_CDR0;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_GetConvertedDataCH1
//* \brief Return the Channel 1 Converted Data
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_GetConvertedDataCH1 (AT91PS_ADC pADC	// pointer to a ADC controller
  )
{
  return pADC->ADC_CDR1;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_GetConvertedDataCH2
//* \brief Return the Channel 2 Converted Data
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_GetConvertedDataCH2 (AT91PS_ADC pADC	// pointer to a ADC controller
  )
{
  return pADC->ADC_CDR2;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_GetConvertedDataCH3
//* \brief Return the Channel 3 Converted Data
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_GetConvertedDataCH3 (AT91PS_ADC pADC	// pointer to a ADC controller
  )
{
  return pADC->ADC_CDR3;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_GetConvertedDataCH4
//* \brief Return the Channel 4 Converted Data
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_GetConvertedDataCH4 (AT91PS_ADC pADC	// pointer to a ADC controller
  )
{
  return pADC->ADC_CDR4;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_GetConvertedDataCH5
//* \brief Return the Channel 5 Converted Data
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_GetConvertedDataCH5 (AT91PS_ADC pADC	// pointer to a ADC controller
  )
{
  return pADC->ADC_CDR5;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_GetConvertedDataCH6
//* \brief Return the Channel 6 Converted Data
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_GetConvertedDataCH6 (AT91PS_ADC pADC	// pointer to a ADC controller
  )
{
  return pADC->ADC_CDR6;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_GetConvertedDataCH7
//* \brief Return the Channel 7 Converted Data
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_ADC_GetConvertedDataCH7 (AT91PS_ADC pADC	// pointer to a ADC controller
  )
{
  return pADC->ADC_CDR7;
}

/* *****************************************************************************
                SOFTWARE API FOR SSC
   ***************************************************************************** */
//* Define the standard I2S mode configuration

//* Configuration to set in the SSC Transmit Clock Mode Register
//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
//*                       nb_slot_by_frame : number of channels
#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
									   AT91C_SSC_CKS_DIV   +\
                            		   AT91C_SSC_CKO_CONTINOUS      +\
                            		   AT91C_SSC_CKG_NONE    +\
                                       AT91C_SSC_START_FALL_RF +\
                           			   AT91C_SSC_STTOUT  +\
                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))


//* Configuration to set in the SSC Transmit Frame Mode Register
//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
//*                      nb_slot_by_frame : number of channels
#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
									(nb_bit_by_slot-1)  +\
                            		AT91C_SSC_MSBF   +\
                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
                            		AT91C_SSC_FSOS_NEGATIVE)


//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_SetBaudrate
//* \brief Set the baudrate according to the CPU clock
//*----------------------------------------------------------------------------
extern void AT91F_SSC_SetBaudrate (AT91PS_SSC pSSC,	// \arg pointer to a SSC controller
				   unsigned int mainClock,	// \arg peripheral clock
				   unsigned int speed);	// \arg SSC baudrate

//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_Configure
//* \brief Configure SSC
//*----------------------------------------------------------------------------
extern void AT91F_SSC_Configure (AT91PS_SSC pSSC,	// \arg pointer to a SSC controller
				 unsigned int syst_clock,	// \arg System Clock Frequency
				 unsigned int baud_rate,	// \arg Expected Baud Rate Frequency
				 unsigned int clock_rx,	// \arg Receiver Clock Parameters
				 unsigned int mode_rx,	// \arg mode Register to be programmed
				 unsigned int clock_tx,	// \arg Transmitter Clock Parameters
				 unsigned int mode_tx);	// \arg mode Register to be programmed

//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_EnableRx
//* \brief Enable receiving datas
//*----------------------------------------------------------------------------
static inline void
AT91F_SSC_EnableRx (AT91PS_SSC pSSC)	// \arg pointer to a SSC controller
{
  //* Enable receiver
  pSSC->SSC_CR = AT91C_SSC_RXEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_DisableRx
//* \brief Disable receiving datas
//*----------------------------------------------------------------------------
static inline void
AT91F_SSC_DisableRx (AT91PS_SSC pSSC)	// \arg pointer to a SSC controller
{
  //* Disable receiver
  pSSC->SSC_CR = AT91C_SSC_RXDIS;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_EnableTx
//* \brief Enable sending datas
//*----------------------------------------------------------------------------
static inline void
AT91F_SSC_EnableTx (AT91PS_SSC pSSC)	// \arg pointer to a SSC controller
{
  //* Enable  transmitter
  pSSC->SSC_CR = AT91C_SSC_TXEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_DisableTx
//* \brief Disable sending datas
//*----------------------------------------------------------------------------
static inline void
AT91F_SSC_DisableTx (AT91PS_SSC pSSC)	// \arg pointer to a SSC controller
{
  //* Disable  transmitter
  pSSC->SSC_CR = AT91C_SSC_TXDIS;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_EnableIt
//* \brief Enable SSC IT
//*----------------------------------------------------------------------------
static inline void
AT91F_SSC_EnableIt (AT91PS_SSC pSSC,	// \arg pointer to a SSC controller
		    unsigned int flag)	// \arg IT to be enabled
{
  //* Write to the IER register
  pSSC->SSC_IER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_DisableIt
//* \brief Disable SSC IT
//*----------------------------------------------------------------------------
static inline void
AT91F_SSC_DisableIt (AT91PS_SSC pSSC,	// \arg pointer to a SSC controller
		     unsigned int flag)	// \arg IT to be disabled
{
  //* Write to the IDR register
  pSSC->SSC_IDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_ReceiveFrame
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_SSC_ReceiveFrame (AT91PS_SSC pSSC,
			unsigned char *pBuffer,
			unsigned int szBuffer,
			unsigned char *pNextBuffer, unsigned int szNextBuffer)
{
  return AT91F_PDC_ReceiveFrame ((AT91PS_PDC) & (pSSC->SSC_RPR),
				 pBuffer,
				 szBuffer, pNextBuffer, szNextBuffer);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_SendFrame
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_SSC_SendFrame (AT91PS_SSC pSSC,
		     const unsigned char *pBuffer,
		     unsigned int szBuffer,
		     const unsigned char *pNextBuffer,
		     unsigned int szNextBuffer)
{
  return AT91F_PDC_SendFrame ((AT91PS_PDC) & (pSSC->SSC_RPR),
			      pBuffer, szBuffer, pNextBuffer, szNextBuffer);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_GetInterruptMaskStatus
//* \brief Return SSC Interrupt Mask Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_SSC_GetInterruptMaskStatus (	// \return SSC Interrupt Mask Status
				   AT91PS_SSC pSsc)	// \arg  pointer to a SSC controller
{
  return pSsc->SSC_IMR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_IsInterruptMasked
//* \brief Test if SSC Interrupt is Masked 
//*----------------------------------------------------------------------------
static inline int
AT91F_SSC_IsInterruptMasked (AT91PS_SSC pSsc,	// \arg  pointer to a SSC controller
			     unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_SSC_GetInterruptMaskStatus (pSsc) & flag);
}

/* *****************************************************************************
                SOFTWARE API FOR USART
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_US_Baudrate
//* \brief Calculate the baudrate
//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
                        AT91C_US_NBSTOP_1_BIT + \
                        AT91C_US_PAR_NONE + \
                        AT91C_US_CHRL_8_BITS + \
                        AT91C_US_CLKS_CLOCK )

//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
                            AT91C_US_NBSTOP_1_BIT + \
                            AT91C_US_PAR_NONE + \
                            AT91C_US_CHRL_8_BITS + \
                            AT91C_US_CLKS_EXT )

//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
                       AT91C_US_USMODE_NORMAL + \
                       AT91C_US_NBSTOP_1_BIT + \
                       AT91C_US_PAR_NONE + \
                       AT91C_US_CHRL_8_BITS + \
                       AT91C_US_CLKS_CLOCK )

//* SCK used Label
#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)

//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
					   		 AT91C_US_CLKS_CLOCK +\
                       		 AT91C_US_NBSTOP_1_BIT + \
                       		 AT91C_US_PAR_EVEN + \
                       		 AT91C_US_CHRL_8_BITS + \
                       		 AT91C_US_CKLO +\
                       		 AT91C_US_OVER)

//* Standard IRDA mode
#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
                            AT91C_US_NBSTOP_1_BIT + \
                            AT91C_US_PAR_NONE + \
                            AT91C_US_CHRL_8_BITS + \
                            AT91C_US_CLKS_CLOCK )

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_Baudrate
//* \brief Caluculate baud_value according to the main clock and the baud rate
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_US_Baudrate (const unsigned int main_clock,	// \arg peripheral clock
		   const unsigned int baud_rate)	// \arg UART baudrate
{
  unsigned int baud_value = ((main_clock * 10) / (baud_rate * 16));
  if ((baud_value % 10) >= 5)
    baud_value = (baud_value / 10) + 1;
  else
    baud_value /= 10;
  return baud_value;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_SetBaudrate
//* \brief Set the baudrate according to the CPU clock
//*----------------------------------------------------------------------------
static inline void
AT91F_US_SetBaudrate (AT91PS_USART pUSART,	// \arg pointer to a USART controller
		      unsigned int mainClock,	// \arg peripheral clock
		      unsigned int speed)	// \arg UART baudrate
{
  //* Define the baud rate divisor register
  pUSART->US_BRGR = AT91F_US_Baudrate (mainClock, speed);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_SetTimeguard
//* \brief Set USART timeguard
//*----------------------------------------------------------------------------
static inline void
AT91F_US_SetTimeguard (AT91PS_USART pUSART,	// \arg pointer to a USART controller
		       unsigned int timeguard)	// \arg timeguard value
{
  //* Write the Timeguard Register
  pUSART->US_TTGR = timeguard;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_EnableIt
//* \brief Enable USART IT
//*----------------------------------------------------------------------------
static inline void
AT91F_US_EnableIt (AT91PS_USART pUSART,	// \arg pointer to a USART controller
		   unsigned int flag)	// \arg IT to be enabled
{
  //* Write to the IER register
  pUSART->US_IER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_DisableIt
//* \brief Disable USART IT
//*----------------------------------------------------------------------------
static inline void
AT91F_US_DisableIt (AT91PS_USART pUSART,	// \arg pointer to a USART controller
		    unsigned int flag)	// \arg IT to be disabled
{
  //* Write to the IER register
  pUSART->US_IDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_Configure
//* \brief Configure USART
//*----------------------------------------------------------------------------
extern void AT91F_US_Configure (AT91PS_USART pUSART,	// \arg pointer to a USART controller
				unsigned int mainClock,	// \arg peripheral clock
				unsigned int mode,	// \arg mode Register to be programmed
				unsigned int baudRate,	// \arg baudrate to be programmed
				unsigned int timeguard);	// \arg timeguard to be programmed

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_EnableRx
//* \brief Enable receiving characters
//*----------------------------------------------------------------------------
static inline void
AT91F_US_EnableRx (AT91PS_USART pUSART)	// \arg pointer to a USART controller
{
  //* Enable receiver
  pUSART->US_CR = AT91C_US_RXEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_EnableTx
//* \brief Enable sending characters
//*----------------------------------------------------------------------------
static inline void
AT91F_US_EnableTx (AT91PS_USART pUSART)	// \arg pointer to a USART controller
{
  //* Enable  transmitter
  pUSART->US_CR = AT91C_US_TXEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_ResetRx
//* \brief Reset Receiver and re-enable it
//*----------------------------------------------------------------------------
static inline void
AT91F_US_ResetRx (AT91PS_USART pUSART)	// \arg pointer to a USART controller
{
  //* Reset receiver
  pUSART->US_CR = AT91C_US_RSTRX;
  //* Re-Enable receiver
  pUSART->US_CR = AT91C_US_RXEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_ResetTx
//* \brief Reset Transmitter and re-enable it
//*----------------------------------------------------------------------------
static inline void
AT91F_US_ResetTx (AT91PS_USART pUSART)	// \arg pointer to a USART controller
{
  //* Reset transmitter
  pUSART->US_CR = AT91C_US_RSTTX;
  //* Enable transmitter
  pUSART->US_CR = AT91C_US_TXEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_DisableRx
//* \brief Disable Receiver
//*----------------------------------------------------------------------------
static inline void
AT91F_US_DisableRx (AT91PS_USART pUSART)	// \arg pointer to a USART controller
{
  //* Disable receiver
  pUSART->US_CR = AT91C_US_RXDIS;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_DisableTx
//* \brief Disable Transmitter
//*----------------------------------------------------------------------------
static inline void
AT91F_US_DisableTx (AT91PS_USART pUSART)	// \arg pointer to a USART controller
{
  //* Disable transmitter
  pUSART->US_CR = AT91C_US_TXDIS;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_Close
//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
//*----------------------------------------------------------------------------
extern void AT91F_US_Close (AT91PS_USART pUSART);	// \arg pointer to a USART controller

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_TxReady
//* \brief Return 1 if a character can be written in US_THR
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_US_TxReady (AT91PS_USART pUSART)	// \arg pointer to a USART controller
{
  return (pUSART->US_CSR & AT91C_US_TXRDY);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_RxReady
//* \brief Return 1 if a character can be read in US_RHR
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_US_RxReady (AT91PS_USART pUSART)	// \arg pointer to a USART controller
{
  return (pUSART->US_CSR & AT91C_US_RXRDY);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_Error
//* \brief Return the error flag
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_US_Error (AT91PS_USART pUSART)	// \arg pointer to a USART controller
{
  return (pUSART->US_CSR & (AT91C_US_OVRE |	// Overrun error
			    AT91C_US_FRAME |	// Framing error
			    AT91C_US_PARE));	// Parity error
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_PutChar
//* \brief Send a character,does not check if ready to send
//*----------------------------------------------------------------------------
static inline void
AT91F_US_PutChar (AT91PS_USART pUSART, int character)
{
  pUSART->US_THR = (character & 0x1FF);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_GetChar
//* \brief Receive a character,does not check if a character is available
//*----------------------------------------------------------------------------
static inline int
AT91F_US_GetChar (const AT91PS_USART pUSART)
{
  return ((pUSART->US_RHR) & 0x1FF);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_SendFrame
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_US_SendFrame (AT91PS_USART pUSART,
		    const unsigned char *pBuffer,
		    unsigned int szBuffer,
		    const unsigned char *pNextBuffer,
		    unsigned int szNextBuffer)
{
  return AT91F_PDC_SendFrame ((AT91PS_PDC) & (pUSART->US_RPR),
			      pBuffer, szBuffer, pNextBuffer, szNextBuffer);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_ReceiveFrame
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_US_ReceiveFrame (AT91PS_USART pUSART,
		       unsigned char *pBuffer,
		       unsigned int szBuffer,
		       unsigned char *pNextBuffer, unsigned int szNextBuffer)
{
  return AT91F_PDC_ReceiveFrame ((AT91PS_PDC) & (pUSART->US_RPR),
				 pBuffer,
				 szBuffer, pNextBuffer, szNextBuffer);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_SetIrdaFilter
//* \brief Set the value of IrDa filter tregister
//*----------------------------------------------------------------------------
static inline void
AT91F_US_SetIrdaFilter (AT91PS_USART pUSART, unsigned char value)
{
  pUSART->US_IF = value;
}

/* *****************************************************************************
                SOFTWARE API FOR TWI
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_TWI_EnableIt
//* \brief Enable TWI IT
//*----------------------------------------------------------------------------
static inline void
AT91F_TWI_EnableIt (AT91PS_TWI pTWI,	// \arg pointer to a TWI controller
		    unsigned int flag)	// \arg IT to be enabled
{
  //* Write to the IER register
  pTWI->TWI_IER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_TWI_DisableIt
//* \brief Disable TWI IT
//*----------------------------------------------------------------------------
static inline void
AT91F_TWI_DisableIt (AT91PS_TWI pTWI,	// \arg pointer to a TWI controller
		     unsigned int flag)	// \arg IT to be disabled
{
  //* Write to the IDR register
  pTWI->TWI_IDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_TWI_Configure
//* \brief Configure TWI in master mode
//*----------------------------------------------------------------------------
static inline void
AT91F_TWI_Configure (AT91PS_TWI pTWI)	// \arg pointer to a TWI controller
{
  //* Disable interrupts
  pTWI->TWI_IDR = (unsigned int) -1;

  //* Reset peripheral
  pTWI->TWI_CR = AT91C_TWI_SWRST;

  //* Set Master mode
  pTWI->TWI_CR = AT91C_TWI_MSEN;

}

//*----------------------------------------------------------------------------
//* \fn    AT91F_TWI_GetInterruptMaskStatus
//* \brief Return TWI Interrupt Mask Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_TWI_GetInterruptMaskStatus (	// \return TWI Interrupt Mask Status
				   AT91PS_TWI pTwi)	// \arg  pointer to a TWI controller
{
  return pTwi->TWI_IMR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_TWI_IsInterruptMasked
//* \brief Test if TWI Interrupt is Masked 
//*----------------------------------------------------------------------------
static inline int
AT91F_TWI_IsInterruptMasked (AT91PS_TWI pTwi,	// \arg  pointer to a TWI controller
			     unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_TWI_GetInterruptMaskStatus (pTwi) & flag);
}

/* *****************************************************************************
                SOFTWARE API FOR TC
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_TC_InterruptEnable
//* \brief Enable TC Interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_TC_InterruptEnable (AT91PS_TC pTc,	// \arg  pointer to a TC controller
			  unsigned int flag)	// \arg  TC interrupt to be enabled
{
  pTc->TC_IER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_TC_InterruptDisable
//* \brief Disable TC Interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_TC_InterruptDisable (AT91PS_TC pTc,	// \arg  pointer to a TC controller
			   unsigned int flag)	// \arg  TC interrupt to be disabled
{
  pTc->TC_IDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_TC_GetInterruptMaskStatus
//* \brief Return TC Interrupt Mask Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_TC_GetInterruptMaskStatus (	// \return TC Interrupt Mask Status
				  AT91PS_TC pTc)	// \arg  pointer to a TC controller
{
  return pTc->TC_IMR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_TC_IsInterruptMasked
//* \brief Test if TC Interrupt is Masked 
//*----------------------------------------------------------------------------
static inline int
AT91F_TC_IsInterruptMasked (AT91PS_TC pTc,	// \arg  pointer to a TC controller
			    unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_TC_GetInterruptMaskStatus (pTc) & flag);
}

/* *****************************************************************************
                SOFTWARE API FOR PWMC
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_PWM_GetStatus
//* \brief Return PWM Interrupt Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PWMC_GetStatus (		// \return PWM Interrupt Status
		       AT91PS_PWMC pPWM)	// pointer to a PWM controller
{
  return pPWM->PWMC_SR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PWM_InterruptEnable
//* \brief Enable PWM Interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_PWMC_InterruptEnable (AT91PS_PWMC pPwm,	// \arg  pointer to a PWM controller
			    unsigned int flag)	// \arg  PWM interrupt to be enabled
{
  pPwm->PWMC_IER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PWM_InterruptDisable
//* \brief Disable PWM Interrupt
//*----------------------------------------------------------------------------
static inline void
AT91F_PWMC_InterruptDisable (AT91PS_PWMC pPwm,	// \arg  pointer to a PWM controller
			     unsigned int flag)	// \arg  PWM interrupt to be disabled
{
  pPwm->PWMC_IDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PWM_GetInterruptMaskStatus
//* \brief Return PWM Interrupt Mask Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PWMC_GetInterruptMaskStatus (	// \return PWM Interrupt Mask Status
				    AT91PS_PWMC pPwm)	// \arg  pointer to a PWM controller
{
  return pPwm->PWMC_IMR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PWM_IsInterruptMasked
//* \brief Test if PWM Interrupt is Masked
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PWMC_IsInterruptMasked (AT91PS_PWMC pPWM,	// \arg  pointer to a PWM controller
			      unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PWMC_GetInterruptMaskStatus (pPWM) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PWM_IsStatusSet
//* \brief Test if PWM Interrupt is Set
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_PWMC_IsStatusSet (AT91PS_PWMC pPWM,	// \arg  pointer to a PWM controller
			unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_PWMC_GetStatus (pPWM) & flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PWM_CfgChannel
//* \brief Test if PWM Interrupt is Set
//*----------------------------------------------------------------------------
static inline void
AT91F_PWMC_CfgChannel (AT91PS_PWMC pPWM,	// \arg  pointer to a PWM controller
		       unsigned int channelId,	// \arg PWM channel ID
		       unsigned int mode,	// \arg  PWM mode
		       unsigned int period,	// \arg PWM period
		       unsigned int duty)	// \arg PWM duty cycle
{
  pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
  pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
  pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PWM_StartChannel
//* \brief Enable channel
//*----------------------------------------------------------------------------
static inline void
AT91F_PWMC_StartChannel (AT91PS_PWMC pPWM,	// \arg  pointer to a PWM controller
			 unsigned int flag)	// \arg  Channels IDs to be enabled
{
  pPWM->PWMC_ENA = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PWM_StopChannel
//* \brief Disable channel
//*----------------------------------------------------------------------------
static inline void
AT91F_PWMC_StopChannel (AT91PS_PWMC pPWM,	// \arg  pointer to a PWM controller
			unsigned int flag)	// \arg  Channels IDs to be enabled
{
  pPWM->PWMC_DIS = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PWM_UpdateChannel
//* \brief Update Period or Duty Cycle
//*----------------------------------------------------------------------------
static inline void
AT91F_PWMC_UpdateChannel (AT91PS_PWMC pPWM,	// \arg  pointer to a PWM controller
			  unsigned int channelId,	// \arg PWM channel ID
			  unsigned int update)	// \arg  Channels IDs to be enabled
{
  pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
}

/* *****************************************************************************
                SOFTWARE API FOR UDP
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_EnableIt
//* \brief Enable UDP IT
//*----------------------------------------------------------------------------
static inline void
AT91F_UDP_EnableIt (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		    unsigned int flag)	// \arg IT to be enabled
{
  //* Write to the IER register
  pUDP->UDP_IER = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_DisableIt
//* \brief Disable UDP IT
//*----------------------------------------------------------------------------
static inline void
AT91F_UDP_DisableIt (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		     unsigned int flag)	// \arg IT to be disabled
{
  //* Write to the IDR register
  pUDP->UDP_IDR = flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_SetAddress
//* \brief Set UDP functional address
//*----------------------------------------------------------------------------
static inline void
AT91F_UDP_SetAddress (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		      unsigned char address)	// \arg new UDP address
{
  pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_EnableEp
//* \brief Enable Endpoint
//*----------------------------------------------------------------------------
static inline void
AT91F_UDP_EnableEp (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		    unsigned char endpoint)	// \arg endpoint number
{
  pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_DisableEp
//* \brief Enable Endpoint
//*----------------------------------------------------------------------------
static inline void
AT91F_UDP_DisableEp (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		     unsigned char endpoint)	// \arg endpoint number
{
  pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_SetState
//* \brief Set UDP Device state
//*----------------------------------------------------------------------------
static inline void
AT91F_UDP_SetState (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		    unsigned int flag)	// \arg new UDP address
{
  pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
  pUDP->UDP_GLBSTATE |= flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_GetState
//* \brief return UDP Device state
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_UDP_GetState (		// \return the UDP device state
		     AT91PS_UDP pUDP)	// \arg pointer to a UDP controller
{
  return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_ResetEp
//* \brief Reset UDP endpoint
//*----------------------------------------------------------------------------
static inline void
AT91F_UDP_ResetEp (		// \return the UDP device state
		    AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		    unsigned int flag)	// \arg Endpoints to be reset
{
  pUDP->UDP_RSTEP = flag;
  pUDP->UDP_RSTEP = 0;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_EpStall
//* \brief Endpoint will STALL requests
//*----------------------------------------------------------------------------
static inline void
AT91F_UDP_EpStall (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		   unsigned char endpoint)	// \arg endpoint number
{
  pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_EpWrite
//* \brief Write value in the DPR
//*----------------------------------------------------------------------------
static inline void
AT91F_UDP_EpWrite (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		   unsigned char endpoint,	// \arg endpoint number
		   unsigned char value)	// \arg value to be written in the DPR
{
  pUDP->UDP_FDR[endpoint] = value;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_EpRead
//* \brief Return value from the DPR
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_UDP_EpRead (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		  unsigned char endpoint)	// \arg endpoint number
{
  return pUDP->UDP_FDR[endpoint];
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_EpEndOfWr
//* \brief Notify the UDP that values in DPR are ready to be sent
//*----------------------------------------------------------------------------
static inline void
AT91F_UDP_EpEndOfWr (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		     unsigned char endpoint)	// \arg endpoint number
{
  pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_EpClear
//* \brief Clear flag in the endpoint CSR register
//*----------------------------------------------------------------------------
static inline void
AT91F_UDP_EpClear (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		   unsigned char endpoint,	// \arg endpoint number
		   unsigned int flag)	// \arg flag to be cleared
{
  pUDP->UDP_CSR[endpoint] &= ~(flag);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_EpSet
//* \brief Set flag in the endpoint CSR register
//*----------------------------------------------------------------------------
static inline void
AT91F_UDP_EpSet (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		 unsigned char endpoint,	// \arg endpoint number
		 unsigned int flag)	// \arg flag to be cleared
{
  pUDP->UDP_CSR[endpoint] |= flag;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_EpStatus
//* \brief Return the endpoint CSR register
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_UDP_EpStatus (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller
		    unsigned char endpoint)	// \arg endpoint number
{
  return pUDP->UDP_CSR[endpoint];
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_GetInterruptMaskStatus
//* \brief Return UDP Interrupt Mask Status
//*----------------------------------------------------------------------------
static inline unsigned int
AT91F_UDP_GetInterruptMaskStatus (AT91PS_UDP pUdp)	// \arg  pointer to a UDP controller
{
  return pUdp->UDP_IMR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_IsInterruptMasked
//* \brief Test if UDP Interrupt is Masked 
//*----------------------------------------------------------------------------
static inline int
AT91F_UDP_IsInterruptMasked (AT91PS_UDP pUdp,	// \arg  pointer to a UDP controller
			     unsigned int flag)	// \arg  flag to be tested
{
  return (AT91F_UDP_GetInterruptMaskStatus (pUdp) & flag);
}

// ----------------------------------------------------------------------------
//  \fn    AT91F_UDP_InterruptStatusRegister
//  \brief Return the Interrupt Status Register
// ----------------------------------------------------------------------------
static inline unsigned int
AT91F_UDP_InterruptStatusRegister (AT91PS_UDP pUDP)	// \arg  pointer to a UDP controller
{
  return pUDP->UDP_ISR;
}

// ----------------------------------------------------------------------------
//  \fn    AT91F_UDP_InterruptClearRegister
//  \brief Clear Interrupt Register
// ----------------------------------------------------------------------------
static inline void
AT91F_UDP_InterruptClearRegister (AT91PS_UDP pUDP,	// \arg pointer to UDP controller
				  unsigned int flag)	// \arg IT to be cleat
{
  pUDP->UDP_ICR = flag;
}

// ----------------------------------------------------------------------------
//  \fn    AT91F_UDP_EnableTransceiver
//  \brief Enable transceiver
// ----------------------------------------------------------------------------
static inline void
AT91F_UDP_EnableTransceiver (AT91PS_UDP pUDP)	// \arg  pointer to a UDP controller
{
  pUDP->UDP_TXVC &= ~AT91C_UDP_TXVDIS;
}

// ----------------------------------------------------------------------------
//  \fn    AT91F_UDP_DisableTransceiver
//  \brief Disable transceiver
// ----------------------------------------------------------------------------
static inline void
AT91F_UDP_DisableTransceiver (AT91PS_UDP pUDP)	// \arg  pointer to a UDP controller
{
  pUDP->UDP_TXVC = AT91C_UDP_TXVDIS;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_DBGU_CfgPMC
//* \brief Enable Peripheral clock in PMC for  DBGU
//*----------------------------------------------------------------------------
static inline void
AT91F_DBGU_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_SYS));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_DBGU_CfgPIO
//* \brief Configure PIO controllers to drive DBGU signals
//*----------------------------------------------------------------------------
static inline void
AT91F_DBGU_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       ((unsigned int) AT91C_PA9_DRXD) | ((unsigned int) AT91C_PA10_DTXD),	// Peripheral A
		       0);	// Peripheral B
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_CfgPMC
//* \brief Enable Peripheral clock in PMC for  PMC
//*----------------------------------------------------------------------------
static inline void
AT91F_PMC_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_SYS));
}

#if !defined(__AT91SAM7SE512__)
//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_CfgPIO
//* \brief Configure PIO controllers to drive PMC signals
//*----------------------------------------------------------------------------
static inline void
AT91F_PMC_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       0,	// Peripheral A
		       ((unsigned int) AT91C_PA6_PCK0) | ((unsigned int) AT91C_PA18_PCK2) | ((unsigned int) AT91C_PA31_PCK2) | ((unsigned int) AT91C_PA21_PCK1) | ((unsigned int) AT91C_PA17_PCK1));	// Peripheral B
}
#endif

//*----------------------------------------------------------------------------
//* \fn    AT91F_VREG_CfgPMC
//* \brief Enable Peripheral clock in PMC for  VREG
//*----------------------------------------------------------------------------
static inline void
AT91F_VREG_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_SYS));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_RSTC_CfgPMC
//* \brief Enable Peripheral clock in PMC for  RSTC
//*----------------------------------------------------------------------------
static inline void
AT91F_RSTC_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_SYS));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_CfgPMC
//* \brief Enable Peripheral clock in PMC for  SSC
//*----------------------------------------------------------------------------
static inline void
AT91F_SSC_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_SSC));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_SSC_CfgPIO
//* \brief Configure PIO controllers to drive SSC signals
//*----------------------------------------------------------------------------
static inline void
AT91F_SSC_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       ((unsigned int) AT91C_PA19_RK) | ((unsigned int) AT91C_PA16_TK) | ((unsigned int) AT91C_PA15_TF) | ((unsigned int) AT91C_PA18_RD) | ((unsigned int) AT91C_PA20_RF) | ((unsigned int) AT91C_PA17_TD),	// Peripheral A
		       0);	// Peripheral B
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_WDTC_CfgPMC
//* \brief Enable Peripheral clock in PMC for  WDTC
//*----------------------------------------------------------------------------
static inline void
AT91F_WDTC_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_SYS));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US1_CfgPMC
//* \brief Enable Peripheral clock in PMC for  US1
//*----------------------------------------------------------------------------
static inline void
AT91F_US1_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_US1));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US1_CfgPIO
//* \brief Configure PIO controllers to drive US1 signals
//*----------------------------------------------------------------------------
static inline void
AT91F_US1_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       ((unsigned int) AT91C_PA29_RI1) | ((unsigned int) AT91C_PA26_DCD1) | ((unsigned int) AT91C_PA28_DSR1) | ((unsigned int) AT91C_PA27_DTR1) | ((unsigned int) AT91C_PA23_SCK1) | ((unsigned int) AT91C_PA24_RTS1) | ((unsigned int) AT91C_PA22_TXD1) | ((unsigned int) AT91C_PA21_RXD1) | ((unsigned int) AT91C_PA25_CTS1),	// Peripheral A
		       0);	// Peripheral B
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US0_CfgPMC
//* \brief Enable Peripheral clock in PMC for  US0
//*----------------------------------------------------------------------------
static inline void
AT91F_US0_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_US0));
}

#if !defined(__AT91SAM7SE512__)
//*----------------------------------------------------------------------------
//* \fn    AT91F_US0_CfgPIO
//* \brief Configure PIO controllers to drive US0 signals
//*----------------------------------------------------------------------------
static inline void
AT91F_US0_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       ((unsigned int) AT91C_PA5_RXD0) | ((unsigned int) AT91C_PA8_CTS0) | ((unsigned int) AT91C_PA7_RTS0) | ((unsigned int) AT91C_PA6_TXD0),	// Peripheral A
		       ((unsigned int) AT91C_PA2_SCK0));	// Peripheral B
}
#endif

//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_CfgPMC
//* \brief Enable Peripheral clock in PMC for  SPI
//*----------------------------------------------------------------------------
static inline void
AT91F_SPI_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_SPI));
}

#if !defined(__AT91SAM7SE512__)
//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_CfgPIO
//* \brief Configure PIO controllers to drive SPI signals
//*----------------------------------------------------------------------------
static inline void
AT91F_SPI_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       ((unsigned int) AT91C_PA13_MOSI) | ((unsigned int) AT91C_PA31_NPCS1) | ((unsigned int) AT91C_PA14_SPCK) | ((unsigned int) AT91C_PA11_NPCS0) | ((unsigned int) AT91C_PA12_MISO),	// Peripheral A
		       ((unsigned int) AT91C_PA9_NPCS1) | ((unsigned int) AT91C_PA22_NPCS3) | ((unsigned int) AT91C_PA3_NPCS3) | ((unsigned int) AT91C_PA5_NPCS3) | ((unsigned int) AT91C_PA10_NPCS2) | ((unsigned int) AT91C_PA30_NPCS2));	// Peripheral B
}
#endif

//*----------------------------------------------------------------------------
//* \fn    AT91F_PITC_CfgPMC
//* \brief Enable Peripheral clock in PMC for  PITC
//*----------------------------------------------------------------------------
static inline void
AT91F_PITC_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_SYS));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_CfgPMC
//* \brief Enable Peripheral clock in PMC for  AIC
//*----------------------------------------------------------------------------
static inline void
AT91F_AIC_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_FIQ) |
			       ((unsigned int) 1 << AT91C_ID_IRQ0) |
			       ((unsigned int) 1 << AT91C_ID_IRQ1));
}

#if !defined(__AT91SAM7SE512__)
//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_CfgPIO
//* \brief Configure PIO controllers to drive AIC signals
//*----------------------------------------------------------------------------
static inline void
AT91F_AIC_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       ((unsigned int) AT91C_PA30_IRQ1),	// Peripheral A
		       ((unsigned int) AT91C_PA20_IRQ0) | ((unsigned int) AT91C_PA19_FIQ));	// Peripheral B
}
#endif

//*----------------------------------------------------------------------------
//* \fn    AT91F_TWI_CfgPMC
//* \brief Enable Peripheral clock in PMC for  TWI
//*----------------------------------------------------------------------------
static inline void
AT91F_TWI_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_TWI));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_TWI_CfgPIO
//* \brief Configure PIO controllers to drive TWI signals
//*----------------------------------------------------------------------------
static inline void
AT91F_TWI_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       ((unsigned int) AT91C_PA4_TWCK) | ((unsigned int) AT91C_PA3_TWD),	// Peripheral A
		       0);	// Peripheral B
}

#if !defined(__AT91SAM7SE512__)
//*----------------------------------------------------------------------------
//* \fn    AT91F_PWMC_CH3_CfgPIO
//* \brief Configure PIO controllers to drive PWMC_CH3 signals
//*----------------------------------------------------------------------------
static inline void
AT91F_PWMC_CH3_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       0,	// Peripheral A
		       ((unsigned int) AT91C_PA7_PWM3) | ((unsigned int) AT91C_PA14_PWM3));	// Peripheral B
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PWMC_CH2_CfgPIO
//* \brief Configure PIO controllers to drive PWMC_CH2 signals
//*----------------------------------------------------------------------------
static inline void
AT91F_PWMC_CH2_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       ((unsigned int) AT91C_PA2_PWM2),	// Peripheral A
		       ((unsigned int) AT91C_PA13_PWM2) | ((unsigned int) AT91C_PA25_PWM2));	// Peripheral B
}


//*----------------------------------------------------------------------------
//* \fn    AT91F_PWMC_CH1_CfgPIO
//* \brief Configure PIO controllers to drive PWMC_CH1 signals
//*----------------------------------------------------------------------------
static inline void
AT91F_PWMC_CH1_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       ((unsigned int) AT91C_PA1_PWM1),	// Peripheral A
		       ((unsigned int) AT91C_PA24_PWM1) | ((unsigned int) AT91C_PA12_PWM1));	// Peripheral B
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PWMC_CH0_CfgPIO
//* \brief Configure PIO controllers to drive PWMC_CH0 signals
//*----------------------------------------------------------------------------
static inline void
AT91F_PWMC_CH0_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       ((unsigned int) AT91C_PA0_PWM0),	// Peripheral A
		       ((unsigned int) AT91C_PA23_PWM0) | ((unsigned int) AT91C_PA11_PWM0));	// Peripheral B
}
#endif

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_CfgPMC
//* \brief Enable Peripheral clock in PMC for  ADC
//*----------------------------------------------------------------------------
static inline void
AT91F_ADC_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_ADC));
}

#if !defined(__AT91SAM7SE512__)
//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC_CfgPIO
//* \brief Configure PIO controllers to drive ADC signals
//*----------------------------------------------------------------------------
static inline void
AT91F_ADC_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       0,	// Peripheral A
		       ((unsigned int) AT91C_PA8_ADTRG));	// Peripheral B
}
#endif

//*----------------------------------------------------------------------------
//* \fn    AT91F_RTTC_CfgPMC
//* \brief Enable Peripheral clock in PMC for  RTTC
//*----------------------------------------------------------------------------
static inline void
AT91F_RTTC_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_SYS));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UDP_CfgPMC
//* \brief Enable Peripheral clock in PMC for  UDP
//*----------------------------------------------------------------------------
static inline void
AT91F_UDP_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_UDP));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_TC0_CfgPMC
//* \brief Enable Peripheral clock in PMC for  TC0
//*----------------------------------------------------------------------------
static inline void
AT91F_TC0_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_TC0));
}

#if !defined(__AT91SAM7SE512__)
//*----------------------------------------------------------------------------
//* \fn    AT91F_TC0_CfgPIO
//* \brief Configure PIO controllers to drive TC0 signals
//*----------------------------------------------------------------------------
static inline void
AT91F_TC0_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       0,	// Peripheral A
		       ((unsigned int) AT91C_PA0_TIOA0) | ((unsigned int) AT91C_PA4_TCLK0) | ((unsigned int) AT91C_PA1_TIOB0));	// Peripheral B
}
#endif

//*----------------------------------------------------------------------------
//* \fn    AT91F_TC1_CfgPMC
//* \brief Enable Peripheral clock in PMC for  TC1
//*----------------------------------------------------------------------------
static inline void
AT91F_TC1_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_TC1));
}

#if !defined(__AT91SAM7SE512__)
//*----------------------------------------------------------------------------
//* \fn    AT91F_TC1_CfgPIO
//* \brief Configure PIO controllers to drive TC1 signals
//*----------------------------------------------------------------------------
static inline void
AT91F_TC1_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       0,	// Peripheral A
		       ((unsigned int) AT91C_PA15_TIOA1) | ((unsigned int) AT91C_PA28_TCLK1) | ((unsigned int) AT91C_PA16_TIOB1));	// Peripheral B
}
#endif

//*----------------------------------------------------------------------------
//* \fn    AT91F_TC2_CfgPMC
//* \brief Enable Peripheral clock in PMC for  TC2
//*----------------------------------------------------------------------------
static inline void
AT91F_TC2_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_TC2));
}

#if !defined(__AT91SAM7SE512__)
//*----------------------------------------------------------------------------
//* \fn    AT91F_TC2_CfgPIO
//* \brief Configure PIO controllers to drive TC2 signals
//*----------------------------------------------------------------------------
static inline void
AT91F_TC2_CfgPIO (void)
{
  // Configure PIO controllers to periph mode
  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address
		       0,	// Peripheral A
		       ((unsigned int) AT91C_PA27_TIOB2) | ((unsigned int) AT91C_PA26_TIOA2) | ((unsigned int) AT91C_PA29_TCLK2));	// Peripheral B
}
#endif

//*----------------------------------------------------------------------------
//* \fn    AT91F_MC_CfgPMC
//* \brief Enable Peripheral clock in PMC for  MC
//*----------------------------------------------------------------------------
static inline void
AT91F_MC_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_SYS));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PIOA_CfgPMC
//* \brief Enable Peripheral clock in PMC for  PIOA
//*----------------------------------------------------------------------------
static inline void
AT91F_PIOA_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_PIOA));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PWMC_CfgPMC
//* \brief Enable Peripheral clock in PMC for  PWMC
//*----------------------------------------------------------------------------
static inline void
AT91F_PWMC_CfgPMC (void)
{
  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address
			       ((unsigned int) 1 << AT91C_ID_PWMC));
}

#define __ramfunc __attribute__ ((long_call, section (".fastrun")))

#endif // lib_AT91SAM7
